US 12,266,570 B2
Self-aligned interconnect structures and methods of fabrication
Kimin Jun, Portland, OR (US); Souvik Ghosh, Beaverton, OR (US); Willy Rachmady, Beaverton, OR (US); Ashish Agrawal, Hillsboro, OR (US); Siddharth Chouksey, Portland, OR (US); Jessica Torres, Portland, OR (US); Jack Kavalieros, Portland, OR (US); Matthew Metz, Portland, OR (US); Ryan Keech, Portland, OR (US); Koustav Ganguly, Beaverton, OR (US); and Anand Murthy, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,065.
Prior Publication US 2022/0199468 A1, Jun. 23, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 21/76897 (2013.01) [H01L 23/5226 (2013.01); H01L 24/83 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/456 (2013.01); H01L 29/66795 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H01L 29/0847 (2013.01); H01L 29/785 (2013.01); H01L 2224/83048 (2013.01); H01L 2224/83359 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first device level comprising a device structure;
a metallization level above the first device level, the metallization level comprising an interconnect structure coupled to the device structure;
a conductive cap on at least a portion of an uppermost surface of the interconnect structure, the conductive cap comprising an alloy of a metal of the interconnect structure and silicon or germanium; and
a second device level above the conductive cap, the second device level comprising a transistor coupled with the conductive cap, wherein the transistor comprises:
a channel layer comprising a semiconductor material; and
a gate above and below the channel layer, wherein:
the gate is between a source region and a drain region;
a sidewall of the conductive cap is adjacent to a sidewall of a portion of the gate below the channel layer; and
the source region or the drain region is in contact with the conductive cap.