US 12,266,567 B2
Method of forming a barrier layer in an interconnect structure of semiconductor device
Bo-Jhih Shen, Tainan (TW); Yi-Wei Chiu, Kaohsiung (TW); and Hung Jui Chang, Shetou Shiang (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 27, 2022, as Appl. No. 17/731,053.
Application 16/787,891 is a division of application No. 15/653,368, filed on Jul. 18, 2017, granted, now 10,566,232, issued on Feb. 18, 2020.
Application 17/731,053 is a continuation of application No. 16/787,891, filed on Feb. 11, 2020, granted, now 11,335,593.
Claims priority of provisional application 62/508,155, filed on May 18, 2017.
Prior Publication US 2022/0254682 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76843 (2013.01) [H01L 21/02063 (2013.01); H01L 21/2855 (2013.01); H01L 21/76804 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76814 (2013.01); H01L 21/76853 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, the method comprising:
forming an opening through a mask layer, the opening exposing a surface of a conductive feature;
after forming the opening, forming a plasma; and
after forming the opening, bombarding a surface of the mask layer using energy species from the plasma to release reactive species from the mask layer and using the energy species from the plasma to remove residues or by-products on the surface of the conductive feature.