	US 12,266,565 B2
	Integrated chip with an etch-stop layer forming a cavity
Hsi-Wen Tien, Xinfeng Township (TW); Chung-Ju Lee, Hsinchu (TW); Chih Wei Lu, Hsinchu (TW); Hsin-Chieh Yao, Hsinchu (TW); Shau-Lin Shue, Hsinchu (TW); Yu-Teng Dai, New Taipei (TW); and Wei-Hao Liao, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/855,060.
Application 17/855,060 is a division of application No. 16/923,424, filed on Jul. 8, 2020, granted, now 11,482,447.
Prior Publication US 2022/0336263 A1, Oct. 20, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)

CPC H01L 21/7682 (2013.01) [H01L 21/76811 (2013.01); H01L 21/76828 (2013.01); H01L 21/76834 (2013.01); H01L 21/823475 (2013.01); H01L 23/5222 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 2221/1042 (2013.01)]

20 Claims

1. An integrated chip, comprising:

a dielectric layer over a substrate;

a first metal feature over the dielectric layer, the first metal feature having a topmost surface at a first height over the substrate;

a second metal feature over the dielectric layer and spaced apart from the first metal feature, the second metal feature having a topmost surface at the first height over the substrate;

a first dielectric liner segment extending laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer, wherein the first dielectric liner segment extends along a first sidewall of the first metal feature that faces the second metal feature and along a first sidewall of the second metal feature that faces the first metal feature, the first dielectric liner segment having a topmost surface at the first height over the substrate;

a cavity laterally between sidewalls of the first dielectric liner segment and above an upper surface of the first dielectric liner segment;

a sacrificial layer directly between the first metal feature and the first dielectric liner segment, the sacrificial layer having a topmost surface at the first height over the substrate; and

an etch-stop layer having a bottommost surface at the first height over the substrate, wherein the bottommost surface of the etch-stop layer delimits the cavity.

11. An integrated chip, comprising:

a dielectric layer over a substrate;

a first metal feature over a top surface of the dielectric layer;

a second metal feature laterally spaced apart from the first metal feature, the second metal feature extending vertically from above the dielectric layer to directly between sidewalls of the dielectric layer and below a bottom surface of the first metal feature;

a sacrificial layer lining the top surface of the dielectric layer, a first sidewall of the first metal feature, and a first sidewall of the second metal feature;

a first dielectric liner segment lining an upper surface of the sacrificial layer, a first sidewall of the sacrificial layer, and a second sidewall of the sacrificial layer;

a first etch-stop layer having a bottommost surface directly on a topmost surface of the first metal feature, a topmost surface of the second metal feature, a topmost surface of the sacrificial layer, and a topmost surface of the first dielectric liner segment; and

a cavity laterally between the first metal feature and the second metal feature, wherein the cavity is delimited by sidewalls of the first dielectric liner segment, an upper surface of the first dielectric liner segment, and the bottommost surface of the first etch-stop layer.

17. An integrated chip, comprising:

a dielectric layer over a substrate;

a first metal feature having a bottom surface over a top surface of the dielectric layer;

a second metal feature laterally spaced apart from the first metal feature, the second metal feature having a bottom surface below the top surface of the dielectric layer and a top surface above the top surface of the dielectric layer;

a first dielectric liner segment having a bottom surface over the top surface of the dielectric layer, the first dielectric liner segment extending along a sidewall of the first metal feature and along a sidewall of the second metal feature;

a cavity over the dielectric layer and directly between the first metal feature and the second metal feature;

a sacrificial layer directly between the first metal feature and the first dielectric liner segment, directly between the second metal feature and the first dielectric liner segment, and directly between the dielectric layer and the first dielectric liner segment; and

an etch-stop layer comprising a dielectric directly over the first metal feature, the second metal feature, the sacrificial layer, and the first dielectric liner segment,

wherein the first metal feature, the second metal feature, the sacrificial layer, and the first dielectric liner segment directly contact a bottommost surface of the etch-stop layer, and wherein the bottommost surface of the etch-stop layer delimits the cavity.