US 12,266,545 B1
Structures and methods for integrated cold plate in XPUs and memory
Laura Mirkarimi, Sunol, CA (US); Gaius Gillman Fountain, Jr., Youngsville, NC (US); and Belgacem Haba, Saratoga, CA (US)
Assigned to Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed on Sep. 20, 2024, as Appl. No. 18/892,142.
Claims priority of provisional application 63/689,428, filed on Aug. 30, 2024.
Claims priority of provisional application 63/651,843, filed on May 24, 2024.
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/473 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01)
CPC H01L 21/4882 (2013.01) [H01L 23/473 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 80/00 (2023.02); H01L 2225/06589 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
preparing a plurality of semiconductor devices, wherein the plurality of semiconductor devices are encapsulated in a mold material;
removing a portion of the mold material to expose a backside of a first semiconductor device of the plurality of semiconductor devices;
forming a first dielectric layer on the backside of the first semiconductor device;
preparing a first cold plate attached to a first portion of a base plate, wherein the first cold plate comprises a coolant channel; and
directly bonding the base plate to the first dielectric layer on the backside of the first semiconductor device.