US 12,266,539 B2
Method of manufacturing semiconductor devices
Ru-Gun Liu, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Wei-Liang Lin, Hsinchu (TW); Yung-Sung Yen, Hsinchu (TW); Ken-Hsien Hsieh, Hsinchu (TW); and Chin-Hsiang Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/225,623.
Application 18/225,623 is a division of application No. 17/751,361, filed on May 23, 2022, granted, now 11,764,068.
Application 17/751,361 is a continuation of application No. 17/034,043, filed on Sep. 28, 2020, granted, now 11,342,193, issued on May 24, 2022.
Application 17/034,043 is a continuation of application No. 16/240,402, filed on Jan. 4, 2019, granted, now 10,790,155, issued on Sep. 29, 2020.
Claims priority of provisional application 62/690,817, filed on Jun. 27, 2018.
Prior Publication US 2023/0369062 A1, Nov. 16, 2023
Int. Cl. H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/31116 (2013.01) [H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming patterns, the method comprising:
forming an initial pattern including a plurality of opening patterns in a first layer disposed over a substrate;
extending the plurality of opening patterns in a first axis by directional etching to form a plurality of exposed groove patterns in plan view,
wherein in the directional etching, an etching rate of the first layer along the first axis is greater than an etching rate of the first layer along a second axis perpendicular to the first axis, the second axis being horizontal and parallel to the surface of the substrate.
 
9. A method of forming a pattern, the method comprising:
forming a first conductive pattern embedded in a first dielectric layer disposed over a substrate;
forming a first opening and a second opening in the first dielectric layer;
extending the first and second openings in a first axis by directional etching to form a groove pattern;
forming a second conductive pattern by filling the groove pattern with a conductive material,
wherein in the directional etching, an etching rate of the first dielectric layer along the first axis is greater than an etching rate of the first dielectric layer along a second axis perpendicular to the first axis, the second axis being horizontal and parallel to the surface of the substrate.
 
13. A method of manufacturing a semiconductor device, the method comprising:
forming a resist pattern having a plurality of opening patterns over an underlying layer disposed over a substrate;
forming a plurality of openings by etching the underlying layer through the plurality of opening patterns;
extending the plurality of openings in a first axis by directional etching to form a plurality of exposed groove patterns in plan view,
wherein in the directional etching, an etching rate of the underlying layer along the first axis is greater than an etching rate of the underlying layer along a second axis perpendicular to the first axis, the second axis being horizontal and parallel to the surface of the substrate.