	US 12,266,535 B2
	Mask encapsulation to prevent degradation during fabrication of high aspect ratio features
Kapu Sirish Reddy, Portland, OR (US); Jon Henri, West Linn, OR (US); and Francis Sloan Roberts, Portland, OR (US)
Assigned to LAM RESEARH CORPORATION, Fremont, CA (US)
Appl. No. 17/642,918
Filed by Lam Research Corporation, Fremont, CA (US)
PCT Filed Sep. 23, 2020, PCT No. PCT/US2020/052181 § 371(c)(1), (2) Date Mar. 14, 2022, PCT Pub. No. WO2021/067092, PCT Pub. Date Apr. 8, 2021.
Claims priority of provisional application 62/909,073, filed on Oct. 1, 2019.
Prior Publication US 2022/0406610 A1, Dec. 22, 2022
Int. Cl. H01L 21/02 (2006.01); C23C 16/26 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 23/29 (2006.01)

CPC H01L 21/3086 (2013.01) [C23C 16/26 (2013.01); H01L 21/02274 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 23/298 (2013.01)]

20 Claims

1. A method for fabricating a feature into a semiconductor substrate, the method comprising:

(a) encapsulating with an etch-resistant material around an opening and sidewalls of a mask defining the feature nominally etched into the semiconductor substrate;

(b) depositing an amorphous carbon liner on the sidewalls of the mask and sidewalls of the feature;

(c) performing an amorphous carbon liner etch for removing excess amorphous carbon deposited around the opening or the sidewalls of the mask during the deposition of the amorphous carbon liner, the etch-resistant material preventing or mitigating etching of the around the opening and the sidewalls of the mask during the amorphous carbon liner etch; and

(d) performing a feature etch to deepen a depth of the feature into the semiconductor substrate.