US 12,266,527 B1
Directed self-assembly enabled patterning over metal layers using assisting features
Gurpreet Singh, Portland, OR (US); Nityan Labros Nair, Portland, OR (US); Nafees A. Kabir, Portland, OR (US); Eungnak Han, Portland, OR (US); Xuanxuan Chen, Hillsboro, OR (US); Brandon Jay Holybee, Portland, OR (US); Charles Henry Wallace, Portland, OR (US); Paul A. Nyhus, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); Florian Gstrein, Portland, OR (US); David Nathan Shykind, Buxton, OR (US); and Thomas Christopher Hoff, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,406.
Int. Cl. H01L 21/027 (2006.01)
CPC H01L 21/0271 (2013.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a first grating layer comprising a plurality of metal lines separated by a plurality of insulator lines, the metal lines having a pitch, the first grating layer further comprising, in a same plane as the plurality of metal lines and the plurality of insulator lines, an insulator region having a width of at least three times the pitch; and
a second grating layer over the first grating layer, the second grating layer comprising a plurality of lines of a first material separated by a plurality of lines of a second material, adjacent lines of the first material arranged at the pitch, the second grating layer comprising:
a first region formed over the insulator region of the first grating layer; and
a second region, wherein a line of the first material in the first region is offset from a line of the first material in the second region, and an amount of the offset is greater than zero and less than the pitch.