US 12,266,526 B2
Formation of single crystal semiconductors using planar vapor liquid solid epitaxy
Martin Christopher Holland, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Oct. 3, 2023, as Appl. No. 18/480,378.
Application 17/570,116 is a division of application No. 16/671,107, filed on Oct. 31, 2019, granted, now 11,251,042, issued on Feb. 15, 2022.
Application 18/480,378 is a continuation of application No. 17/570,116, filed on Jan. 6, 2022, granted, now 11,784,045.
Prior Publication US 2024/0030027 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/00 (2006.01); C30B 19/10 (2006.01); C30B 19/12 (2006.01); C30B 29/06 (2006.01); C30B 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/02653 (2013.01) [C30B 19/106 (2013.01); C30B 19/12 (2013.01); C30B 29/06 (2013.01); C30B 29/08 (2013.01); H01L 21/02488 (2013.01); H01L 21/02532 (2013.01); H01L 21/02625 (2013.01); H01L 21/02645 (2013.01); H01L 21/7624 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/7838 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a template layer over a substrate, the template layer comprising a dielectric material;
a first transistor comprising:
a first buffer structure over a bottom surface of a first trench in the template layer;
a first single crystal semiconductor structure over the first buffer structure, the first single crystal semiconductor structure comprising a p-channel material;
a first gate structure over a channel portion of the first single crystal semiconductor structure; and
first source/drain structures on opposite sides of the first gate structure; and
a second transistor comprising:
a second buffer structure over a bottom surface of a second trench in the template layer;
a second single crystal semiconductor structure over the second buffer structure, the second single crystal semiconductor structure comprising an n-channel material;
a second gate structure over a channel portion of the second single crystal semiconductor structure; and
second source/drain structures on opposite sides of the second gate structure,
wherein a depth of each of the first trench and the second trench is less than a thickness of the template layer such that sidewalls and a bottom of each of the first buffer structure and the second buffer structure are in contact with the template layer.