US 12,266,523 B2
Parasitic capacitance reduction in GaN-on-silicon devices
Gabriel R. Cueva, Bedford, NH (US); Timothy E. Boles, Tyngsboro, MA (US); and Wayne Mack Struble, Franklin, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Feb. 5, 2024, as Appl. No. 18/432,740.
Application 18/432,740 is a continuation of application No. 17/479,543, filed on Sep. 20, 2021, granted, now 11,929,364.
Application 17/479,543 is a continuation of application No. 16/000,287, filed on Jun. 5, 2018, granted, now 11,158,575, issued on Oct. 26, 2021.
Prior Publication US 2024/0178220 A1, May 30, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/74 (2006.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/8252 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01)
CPC H01L 21/0254 (2013.01) [H01L 21/02381 (2013.01); H01L 21/743 (2013.01); H01L 21/746 (2013.01); H01L 21/7605 (2013.01); H01L 21/76202 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/8252 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H01L 23/66 (2013.01); H01L 27/0605 (2013.01); H01L 29/0649 (2013.01); H01L 29/2003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for making a semiconductor structure, comprising:
forming a trench in an interconnect area of a substrate between a first device area in the semiconductor structure and a second device area in the semiconductor structure;
forming a low dielectric constant material region in the trench, a dielectric constant of the low dielectric constant material region being lower than a dielectric constant of the substrate;
forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench;
forming a first device in the III-nitride material layer in the first device area;
forming a second device in the III-nitride material layer in the second device area; and
forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.