US 12,266,515 B2
Wafer placement table
Tatsuya Kuno, Nagoya (JP); and Seiya Inoue, Handa (JP)
Assigned to NGK INSULATORS, LTD., Nagoya (JP)
Filed by NGK Insulators, Ltd., Nagoya (JP)
Filed on Feb. 24, 2023, as Appl. No. 18/173,889.
Claims priority of application No. 2022-072510 (JP), filed on Apr. 26, 2022.
Prior Publication US 2023/0343566 A1, Oct. 26, 2023
Int. Cl. H01J 37/32 (2006.01); H01L 21/683 (2006.01)
CPC H01J 37/32724 (2013.01) [H01L 21/6833 (2013.01); H01J 2237/002 (2013.01); H01J 2237/2007 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A wafer placement table comprising:
an alumina substrate having a wafer placement surface at an upper surface, and incorporating an electrode;
a brittle cooling substrate which is bonded to a lower surface of the alumina substrate, and in which a refrigerant flow path is formed; and
a ductile connection member stored in a storage hole opened in a lower surface of the cooling substrate in a state of restricted axial rotation and in a state of being engaged with an engagement section of the storage hole, the ductile connection member having a male thread section or a female thread section,
wherein the storage hole is provided in the refrigerant flow path.