US 12,266,507 B2
Impedance-matching method, impedance-matching device, and semiconductor process apparatus
Jing Wei, Beijing (CN); Gang Wei, Beijing (CN); and Yueping Hua, Beijing (CN)
Assigned to BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
Appl. No. 18/248,870
Filed by BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD., Beijing (CN)
PCT Filed Oct. 12, 2021, PCT No. PCT/CN2021/123317
§ 371(c)(1), (2) Date Apr. 13, 2023,
PCT Pub. No. WO2022/078336, PCT Pub. Date Apr. 21, 2022.
Claims priority of application No. 202011089179.4 (CN), filed on Oct. 13, 2020.
Prior Publication US 2023/0386790 A1, Nov. 30, 2023
Int. Cl. H01J 37/32 (2006.01); H05H 1/46 (2006.01)
CPC H01J 37/32183 (2013.01) [H01J 2237/32 (2013.01); H05H 1/46 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An impedance-matching method applied to a semiconductor process apparatus, comprising:
adjusting a parameter value of an adjustable element of an impedance-matching device to a preset initial value at beginning of a process;
adjusting the parameter value of the adjustable element according to a pre-stored optimal matching path corresponding to the process in response to a radio frequency (RF) power supply being powered on, the optimal matching path including parameter values of the adjustable element corresponding to different moments in a preset matching period; and
adjusting the parameter value of the adjustable element using an automatic matching algorithm after reaching end time of the preset matching period until impedance matching is achieved, the optimal matching path being a matching path with a most occurrence number without an extinction phenomenon of N matching paths obtained by performing the automatic matching algorithm for N times.