| CPC G11C 8/08 (2013.01) [G11C 8/10 (2013.01)] | 20 Claims |
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1. A memory circuit, comprising:
a first memory cell on a first layer;
a second memory cell on a second layer different from the first layer;
a first select transistor on a third layer different from the first layer and the second layer;
a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell;
a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction; and
a second source line extending in the first direction, and being coupled to the first select transistor.
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