| CPC G11C 7/222 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 16/20 (2013.01)] | 14 Claims |

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1. A semiconductor memory device comprising:
a NAND string;
a first storage circuit configured to store:
a first unique number uniquely assigned; and
a first chip address having a bit number smaller than that of the first unique number and used to identify the semiconductor memory device from other semiconductor memory devices; and
a first determination circuit configured to externally receive a first command set including a second unique number and a second chip address, and to write the second chip address to the first storage circuit as the first chip address when the second unique number matches the first unique number.
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