CPC G11C 7/1048 (2013.01) [G11C 2207/2254 (2013.01)] | 10 Claims |
1. A memory device comprising:
a resistor coupled between a connection terminal and a ground terminal; and
a controller chip comprising:
a first controller configured to transmit a first controller calibration request;
a second controller configured to transmit a second controller calibration request;
a first set of input/output (I/O) circuits coupled to the first controller;
a second set of I/O circuits coupled to the second controller;
a first calibration circuit coupled to the connection terminal and the first set of I/O circuits, and configured to perform a first controller calibration on the first set of I/O circuits using the resistor;
a second calibration circuit coupled to the connection terminal and the second set of I/O circuits, and configured to perform a second controller calibration on the second set of I/O circuits using the resistor; and
an arbitration circuit coupled to the first controller, the second controller, the first calibration circuit and the second calibration circuit, and configured to instruct the first calibration circuit to perform the first controller calibration in response to the first controller calibration request, and instruct the second calibration circuit to perform the second controller calibration in response to the second controller calibration request, wherein a first period of the first calibration circuit performing the first controller calibration and a second period of the second calibration circuit performing the second controller calibration are non-overlapping.
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