US 12,266,420 B2
Temperature-compensated time estimate for a block to reach a uniform charge loss state
Patrick R. Khayat, San Diego, CA (US); Steven Michael Kientz, Westminster, CO (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Mustafa N. Kaynak, San Diego, CA (US); and Vamsi Pavan Rayaprolu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 14, 2023, as Appl. No. 18/509,088.
Application 18/509,088 is a continuation of application No. 17/675,592, filed on Feb. 18, 2022, granted, now 11,854,649.
Prior Publication US 2024/0079035 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/04 (2006.01); G06F 3/06 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G11C 7/04 (2013.01) [G06F 3/064 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
starting a timer when memory cells associated with a first wordline of a plurality of wordlines of a segment of the memory device are written;
periodically incrementing the timer by a temperature compensated time value;
determining a value of the timer when memory cells associated with a last wordline of the plurality of wordlines of the segment of the memory device are written; and
applying a scaling factor to the value of the timer, wherein the value of the timer, as modified by the scaling factor, represents an estimate of when the segment of the memory device will reach a uniform charge loss state.