a memory array, comprising a plurality of memory cells arranged in rows and columns; and

a driver circuit, coupled to the memory array, arranged to operably write data to the memory array according to write signals; wherein the driver circuit comprises a plurality of row driver circuits each coupled to a corresponding row of the memory cells for receiving and converting respective row data for the corresponding row of the memory cells; wherein:

the memory device further comprises a global driver power circuit coupled to the plurality of memory banks, arranged to operably provide a global driver power to row driver circuits in all of the plurality of memory banks;

each of the memory banks further comprises a local driver power circuit, providing a local driver power for powering row driver circuits in a corresponding memory bank;

the local driver power comprises a first multi-threshold power signal; and

the local driver power circuit comprises a first P-type multi-threshold complementary metal oxide semiconductor (MTCMOS) coupled to a power supply and a control signal, controlled by the control signal to provide the first multi-threshold power signal to the row driver circuits in the corresponding memory bank;

wherein the global driver power circuit comprises a second P-type MTCMOS coupled to the power supply and the control signal, controlled by the control signal to generate a second multi-threshold power signal to an operation stage of each of the row driver circuits in each of the memory banks;

wherein the global driver power circuit further comprises a N-type MTCMOS coupled to a ground voltage source and a complementary control signal, controlled by the complementary control signal to generate a second multi-threshold ground signal to the operation stage of each of the row driver circuits in each of the memory banks.