| CPC G11C 5/063 (2013.01) [G11C 5/08 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01)] | 13 Claims |
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1. A storage array, comprising:
a plurality of bit lines, two bit lines being arranged in one row, and comprising a first bit line and a second bit line;
a plurality of source lines, two source lines being arranged in one row, and comprising a first source line and a second source line; and
storage units and transistors located in each column and each row, each transistor having a first source/drain and a second source/drain;
wherein for any row of the storage array, there are the following connection relationships:
a storage unit in an odd-numbered column has one end connected to the first bit line, and the other end connected to the second source line;
the first source/drain of a transistor in an odd-numbered column is connected to the first source line;
the second source/drain of a transistor in an odd-numbered column is connected to the second source line;
a storage unit in an even-numbered column has one end connected to the second bit line, and the other end connected to the first source line;
the first source/drain of a transistor in an even-numbered column is connected to the second source line; and
the second source/drain of a transistor in an even-numbered column is connected to the first source line.
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