US 12,266,415 B1
Reliable electronic fuse based storage using error correction coding
Kevin William Gorman, Essex Junction, VT (US); Paul J. Grzymkowski, Middlesex, VT (US); and John R. Goss, Essex Junction, VT (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 26, 2023, as Appl. No. 18/101,586.
Claims priority of provisional application 63/326,963, filed on Apr. 4, 2022.
Int. Cl. G11C 29/54 (2006.01); G06F 11/10 (2006.01)
CPC G11C 29/54 (2013.01) [G06F 11/1044 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus for reliable fuse-based storage in an Integrated Circuit (IC), the apparatus comprising:
a plurality of electronic fuses configured to store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits;
an ECC module, configured to apply the ECC scheme to the data bits and corresponding parity bits for correcting errors in the data bits; and
processing logic configured to:
receive, from a Built-In Self-Repair (BISR) controller, a read command for reading given data bits from the electronic fuses; and
respond to the read command while rendering the BISR controller unaware of the ECC scheme, by:
based on the read command, retrieving the access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits;
reading, using the access information, the given data bits and the given parity bits from the given electronic fuses;
applying the ECC scheme to the given data bits and the given parity bits, using the ECC module, to generate corrected data bits; and
outputting the corrected data bits to the BISR controller.