US 12,266,413 B2
Built-in self-test circuit for row hammering in memory
Grigor Tshagharyan, Yerevan (AM); Gurgen Harutyunyan, Yerevan (AM); Arun Kumar, Santa Clara, CA (US); and Yervant Zorian, Santa Clara, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,085.
Prior Publication US 2024/0096435 A1, Mar. 21, 2024
Int. Cl. G11C 29/46 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for testing a chip, the method comprising:
receiving an address range of a dynamic random access memory for testing;
based on determining that a first row of the dynamic random access memory is in the address range, writing, by a built-in self-test (BIST) circuit of the chip and according to a system clock, the first row of the dynamic random access memory with a first set of values;
reading, by the BIST circuit and according to the system clock, a second row of the dynamic random access memory a first plurality of times, wherein the second row is adjacent to the first row;
reading, by the BIST circuit and according to the system clock, a third row of the dynamic random access memory a second plurality of times, wherein the third row is adjacent to the first row and different from the second row;
after reading the second row the first plurality of times and the third row the second plurality of times, reading, by the BIST circuit and according to the system clock, the first row to extract a second set of values from the first row;
based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row; and
writing, according to the system clock, a portion of data to a fourth row of the dynamic random access memory rather than the first row based on designating the first row as a vulnerable row.