US 12,266,412 B2
Content addressable memory and content addressable memory cell
Yi-Hsin Tseng, Hsinchu (TW); Chi-Chang Shuai, Hsinchu (TW); and Yen-Yao Wang, Hsinchu (TW)
Assigned to Faraday Technology Corp., Hsinchu (TW)
Filed by Faraday Technology Corp., Hsinchu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,430.
Claims priority of application No. 112115137 (TW), filed on Apr. 24, 2023.
Prior Publication US 2024/0355408 A1, Oct. 24, 2024
Int. Cl. G11C 15/04 (2006.01); G11C 29/44 (2006.01); G11C 15/00 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 15/04 (2013.01); G11C 15/00 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A content addressable memory, comprising:
a memory cell array, comprising a plurality of content addressable memory cells, wherein each of the content addressable memory cells comprises a memory cell circuit and a comparison circuit; and
a disabling circuit, coupled to the comparison circuits of the content addressable memory cells in a first column of the memory cell array, wherein the disabling circuit is controlled by a repair signal, wherein
in response to the repair signal indicating that the content addressable memory cells in the first column are normal, the disabling circuit enables the comparison circuits of the content addressable memory cells in the first column, so that the comparison circuits in the first column respectively present comparison results on different match lines,
in response to the repair signal indicating that any one of the content addressable memory cells in the first column is defective, the disabling circuit disables the comparison circuits of the content addressable memory cells in the first column, so that the disabled comparison circuits do not affect the different match lines.