US 12,266,410 B2
Methods and systems for improving ECC operation of memories
Christophe Laurent, Agrate Brianza (IT); and Riccardo Muzzetto, Arcore (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/801,467
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Mar. 2, 2021, PCT No. PCT/IB2021/020008
§ 371(c)(1), (2) Date Aug. 22, 2022,
PCT Pub. No. WO2022/185088, PCT Pub. Date Sep. 9, 2022.
Prior Publication US 2024/0194284 A1, Jun. 13, 2024
Int. Cl. G11C 29/42 (2006.01); G11C 29/12 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/52 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method for operating an array of memory cells, the method comprising:
storing user data in a plurality of memory cells of the memory array;
storing parity data associated with the user data in parity cells of the memory array, wherein a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability; and
based on the selected number of used parity cells, performing an ECC operation on the plurality of memory cells; and
writing and/or sensing only the memory cells used to store the user data and the selected parity cells used to store the parity data, wherein the used parity cells are selected between a maximum number and a minimum number and a number of unused parity cells is a difference between the maximum number and the number of used parity cells, and wherein the unused parity cells are not written nor sensed.