US 12,266,408 B2
Vertical fuse memory in one-time program memory cells
Sheng-Chih Lai, Hsinchu County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,278.
Application 18/357,278 is a continuation of application No. 16/885,362, filed on May 28, 2020, granted, now 11,818,882.
Claims priority of provisional application 62/948,908, filed on Dec. 17, 2019.
Prior Publication US 2024/0023327 A1, Jan. 18, 2024
Int. Cl. G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip (IC) memory structure, comprising:
a first conductor over a substrate;
a second conductor over the first conductor, the first conductor being vertically separated from the second conductor by an isolation structure;
a first channel structure arranged on a sidewall of the isolation structure, the first channel structure being vertically between the first conductor and the second conductor; and
a vertical gate electrode disposed along sidewalls of the first conductor, the second conductor, and the first channel structure, the sidewall of the first channel structure facing away from the isolation structure.