| CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory array comprising:
a set of target cells connected to a target wordline;
at least one wordline adjacent to the target wordline; and
for each target cell of the set of target cells, a respective group of adjacent cells adjacent to the target cell, wherein each group of adjacent cells comprises at least one cell connected to the at least one wordline; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a read operation to be initiated with respect to the set of target cells;
obtaining, for each group of adjacent cells, respective cell state information;
assigning, based on the respective cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, wherein each state information bin is associated with a respective group of target cells of the set of target cells; and
determining a set of calibrated read level offsets, wherein each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
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