US 12,266,404 B2
Semiconductor storage device
Hiroshi Maejima, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 2, 2024, as Appl. No. 18/653,785.
Application 16/842,633 is a division of application No. 16/391,041, filed on Apr. 22, 2019, granted, now 10,643,702, issued on May 5, 2020.
Application 18/653,785 is a continuation of application No. 18/354,484, filed on Jul. 18, 2023, granted, now 12,009,032.
Application 18/354,484 is a continuation of application No. 17/565,241, filed on Dec. 29, 2021, granted, now 11,756,623, issued on Sep. 12, 2023.
Application 17/565,241 is a continuation of application No. 17/152,355, filed on Jan. 19, 2021, granted, now 11,244,726, issued on Feb. 8, 2022.
Application 17/152,355 is a continuation of application No. 16/842,633, filed on Apr. 7, 2020, granted, now 10,902,918, issued on Jan. 26, 2021.
Application 16/391,041 is a continuation of application No. 16/022,568, filed on Jun. 28, 2018, granted, now 10,276,241, issued on Apr. 30, 2019.
Application 16/022,568 is a continuation of application No. 15/583,609, filed on May 1, 2017, granted, now 10,014,054, issued on Jul. 3, 2018.
Application 15/583,609 is a continuation of application No. 14/788,629, filed on Jun. 30, 2015, granted, now 9,672,927, issued on Jun. 6, 2017.
Application 14/788,629 is a continuation of application No. 13/784,735, filed on Mar. 4, 2013, granted, now 9,111,592, issued on Aug. 18, 2015.
Claims priority of application No. 2012-144628 (JP), filed on Jun. 27, 2012.
Prior Publication US 2024/0296888 A1, Sep. 5, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of first memory strings disposed in a first memory region;
a plurality of second memory strings disposed in a second memory region;
a plurality of third memory strings disposed in a third memory region;
a first bit line extending in a first direction and over the first memory region, the second memory region, and the third memory region, the first bit line connected to a first subset of the plurality of first memory strings;
a second bit line extending in the first direction and over the first memory region, the second memory region, and the third memory region, the second bit line connected to a first subset of the plurality of second memory strings;
a third bit line disposed between the second memory region and a first circuit in a second direction crossing the first direction, the third bit line overlapped by the second memory region in the second direction;
a fourth bit line disposed between the third memory region and a second circuit in the second direction, the fourth bit line overlapped by the third memory region in the second direction;
a first contact plug extending in the second direction, the first contact plug disposed in a first contact region between the first memory region and the second memory region, the first contact plug connected to the first bit line and the third bit line; and
a second contact plug extending in the second direction, the second contact plug disposed in a second contact region between the second memory region and the third memory region, the second contact plug connected to the second bit line and the fourth bit line.