US 12,266,403 B2
Three-dimensional NAND memory and fabrication method thereof
Di Wang, Hubei (CN); Wenxi Zhou, Hubei (CN); Tingting Zhao, Hubei (CN); and Zhiliang Xia, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 31, 2022, as Appl. No. 17/709,651.
Claims priority of application No. 202110532721.7 (CN), filed on May 17, 2021.
Prior Publication US 2022/0366985 A1, Nov. 17, 2022
Int. Cl. H01L 23/528 (2006.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric stack on a substrate, wherein the first dielectric stack comprises a first dielectric layer and a second dielectric layer alternatingly stacked in a first direction perpendicular to the substrate;
forming a second dielectric stack on the first dielectric stack, wherein the second dielectric stack comprises a third dielectric layer and a fourth dielectric layer stacked in the first direction;
forming an etch-stop layer on the second dielectric stack:
forming a gate line slit (GLS) opening through the etch-stop laver, the second dielectric stack and the first dielectric stack; and
replacing the fourth dielectric layer and the second dielectric layer through the GLS opening with conductive layers to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.