| CPC G11C 11/4094 (2013.01) [H01L 29/7869 (2013.01); H10B 12/00 (2023.02)] | 6 Claims |
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1. A semiconductor device comprising:
a first layer comprising a plurality of processing engines; and
a second layer over the first layer,
wherein the second layer comprises a plurality of embedded memory devices each including a peripheral circuit and a memory cell array,
wherein the memory cell array comprises a plurality of memory cells arranged in a matrix,
wherein each of the plurality of embedded memory devices overlaps with each of the plurality of processing engines,
wherein each of the plurality of processing engines comprises a silicon transistor,
wherein the peripheral circuit comprises a transistor including an oxide semiconductor,
wherein each of the plurality of memory cells comprises a first transistor, a second transistor, and a third transistor,
wherein each of the first transistor, the second transistor, and the third transistor includes a gate, a back gate, and the oxide semiconductor, and
wherein different voltages are input to the back gate of the first transistor, the back gate of the second transistor, and the back gate of the third transistor.
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