a sense amplification circuit, comprising a read node, a complementary read node, a first node, and a second node, wherein in a sense amplification stage and an offset cancellation stage, the first node is configured to receive a high level, and the second node is configured to receive a low level;

an isolation circuit, coupled to the read node, the complementary read node, the bit line, and the complementary bit line, wherein the isolation circuit is configured to: in the sense amplification stage, couple the read node to the bit line and couple the complementary read node to the complementary bit line;

an offset cancellation circuit, coupled to the read node, the complementary read node, the bit line, and the complementary bit line, wherein the offset cancellation circuit is configured to: in the offset cancellation stage, couple the bit line to the complementary read node and couple the complementary bit line to the read node; and

a first power supply circuit, coupled to the first node, and comprising a first power supply and a second power supply, a power supply voltage of the first power supply being higher than a power supply voltage of the second power supply, wherein the first power supply circuit is configured to: couple the first power supply to the first node in the offset cancellation stage, and couple the second power supply to the first node in the sense amplification stage;

wherein the sense amplification circuit comprises:

a first P-type transistor, one of a pair of source/drain terminals of the first P-type transistor being coupled to the first node, the other one of the pair of the source/drain terminals of the first P-type transistor being coupled to the complementary read node, and a gate of the first P-type transistor being coupled to the read node;

a second P-type transistor, one of a pair of source/drain terminals of the second P-type transistor is coupled to the first node, the other one of the pair of the source/drain terminals of the second P-type transistor being coupled to the read node, and a gate of the second P-type transistor being coupled to the complementary read node;

a first N-type transistor, one of a pair of source/drain terminals of the first N-type transistor being coupled to the second node, the other one of the pair of the source/drain terminals of the first N-type transistor being coupled to the complementary read node, and a gate of the first N-type transistor being coupled to the bit line; and

a second N-type transistor, one of a pair of source/drain terminals of the second N-type transistor being coupled to the second node, the other one of the pair of the source/drain terminals of the second N-type transistor being coupled to the read node, and a gate of the second N-type transistor being coupled to the complementary bit line, and the isolation circuit comprises:

a first isolation transistor, one of a pair of source/drain terminals of the first isolation transistor being coupled to the bit line, the other one of the pair of the source/drain terminals of the first isolation transistor being coupled to the read node, and a gate of the first isolation transistor being configured to receive an isolation signal, wherein the first isolation transistor is configured to be turned on based on the isolation signal in the sense amplification stage, to couple the read node to the bit line; and

a second isolation transistor, one of a pair of source/drain terminals of the second isolation transistor being coupled to the complementary bit line, the other one of the pair of the source/drain terminals of the second isolation transistor being coupled to the complementary read node, and a gate of the second isolation transistor being configured to receive an isolation signal, wherein the second isolation transistor is configured to be turned on based on the isolation signal in the sense amplification stage, to couple the complementary read node to the complementary bit line.