US 12,266,395 B2
Memory device and operation method thereof
Kyo-Gil Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 7, 2023, as Appl. No. 18/330,404.
Claims priority of application No. 10-2022-0132901 (KR), filed on Oct. 17, 2022.
Prior Publication US 2024/0127879 A1, Apr. 18, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/4078 (2006.01); G11C 11/4096 (2006.01); G11C 29/46 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4078 (2013.01); G11C 11/4096 (2013.01); G11C 29/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array including a plurality of rows; and
a refresh manager configured to:
initialize a count for a row among the plurality of rows of the memory cell array;
transmit a refresh command to the memory cell array;
write first data into the row when the refresh operation for the memory cell array is a normal refresh operation; and
write second data into at least one word line adjacent to a word line of a row on which row hammering has occurred, when the refresh operation is not the normal refresh operation.