US 12,266,393 B2
Negative capacitance for ferroelectric capacitive memory cell
Takashi Ando, Eastchester, NY (US); Reinaldo Vega, Mahopac, NY (US); David Wolpert, Poughkeepsie, NY (US); and Nicholas Anthony Lanzillo, Wynantskill, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 13, 2022, as Appl. No. 18/065,195.
Prior Publication US 2024/0194236 A1, Jun. 13, 2024
Int. Cl. G11C 11/22 (2006.01); H10B 53/30 (2023.01); H10D 1/68 (2025.01)
CPC G11C 11/221 (2013.01) [G11C 11/2273 (2013.01); H10B 53/30 (2023.02); H10D 1/694 (2025.01); H10D 1/696 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A capacitive memory cell comprising:
a first electrode;
a tunneling barrier layer in direct contact with the first electrode;
a charge trapping layer in direct contact with the tunneling barrier layer, wherein the tunneling barrier layer and the charge trapping layer are configured to store a charge and vary a capacitance of the memory cell;
a ferroelectric layer in direct contact with the charge trapping layer; and
a second electrode in direct contact with the ferroelectric layer.