US 12,266,385 B2
Data storage device having dual actuators and method for emergency power off retract (EPOR) of dual actuators
Brian Johnson, Laguna Hills, CA (US); Jaesoo Byoun, Irvine, CA (US); Gaku Ikedo, Fujisawa (JP); Hideaki Ito, Fujisawa (JP); Naoyuki Kagami, Fujisawa (JP); and Hiroki Watanabe, Fujisawa (JP)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Aug. 9, 2023, as Appl. No. 18/446,637.
Application 18/446,637 is a division of application No. 17/716,312, filed on Apr. 8, 2022, granted, now 11,763,844.
Prior Publication US 2023/0386513 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11B 5/55 (2006.01); G11B 5/48 (2006.01)
CPC G11B 5/5578 (2013.01) [G11B 5/4813 (2013.01); G11B 5/5573 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a first actuator configured to actuate a first read-write head over at least a first disk;
a second actuator configured to actuate a second read-write head over at least a second disk;
a spindle motor configured to rotate the first disk and the second disk; and
one or more processing devices or components, the one or more processing devices or components comprising a system on a chip (SoC) and at least one power large scale integrated circuit (PLSI) that is configured to drive the first and second actuators, and wherein the one or more processing devices or components are configured, individually or in combination, in response to an emergency power off (EPO) event, to:
retract and park the first actuator and the second actuator using an internal supply voltage generated from a back electromotive force (BEMF) voltage of the spindle motor, and
brake the spindle motor,
and
wherein the at least one PLSI is further configured to communicate with the SoC to initiate data egress during the EPO event, and wherein the one or more processing devices or components are further configured, individually or in combination, to:
egress data to non-volatile memory, based at least in part on comparing the internal supply voltage generated from the BEMF voltage to one or more egress throttling threshold voltages.