CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2340/0435 (2013.01)] | 17 Claims |
1. A pixel circuit, comprising a drive sub-circuit, a write sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a second reset sub-circuit and a light-emitting element, wherein
the drive sub-circuit is configured to provide a drive signal to a third node in response to signals at a first node and a second node;
the write sub-circuit is configured to write a signal of a data signal line to the second node or the third node under a control of a signal of a first scanning signal line;
the compensation sub-circuit is configured to compensate a voltage at the first node under the control of the signal of the first scanning signal line;
the first reset sub-circuit is configured to reset the first node under a control of a signal of a reset control signal line; and
the second reset sub-circuit is configured to reset an anode terminal of the light-emitting element under a control of a signal of a second scanning signal line,
wherein the compensation sub-circuit comprises a third transistor and a first capacitor, the drive sub-circuit comprises a fourth transistor, and the write sub-circuit comprises a fifth transistor;
a control electrode of the third transistor is connected with the first scanning signal line, a first electrode of the third transistor is connected with the second node, and a second electrode of the third transistor is connected with the first node;
one terminal of the first capacitor is connected with the first node, and another terminal of the first capacitor is connected with the anode terminal of the light-emitting element;
a control electrode of the fourth transistor is connected with the first node, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with the third node; and
a control electrode of the fifth transistor is connected with the first scanning signal line, a first electrode of the fifth transistor is connected with the data signal line, and a second electrode of the fifth transistor is connected with the third node.
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