a plurality of pixel circuit rows and a plurality of pixel circuit columns arranged as an array,

wherein:

each of the plurality of pixel circuit rows includes a first pixel circuit and a second pixel circuit, the first pixel circuit is electrically connected to a first scan line and the second pixel circuit is electrically connected to a second scan line;

first pixel circuits in a same column of the plurality of pixel circuit columns are electrically connected to the first data line, and second pixel circuits in a same column of the plurality of pixel circuit columns are electrically connected to the second data line; and

a first scan signal on the first scan line is configured to control whether a first data signal on the first data line is written to the first pixel circuit, and a second scan signal on the second scan line is configured to control whether a second data signal on the second data line is written to the second pixel circuit.