US 12,266,184 B2
Surveillance cameras implemented using integrated circuit devices having analog inference capability
Poorna Kale, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 8, 2022, as Appl. No. 17/940,929.
Prior Publication US 2024/0087323 A1, Mar. 14, 2024
Int. Cl. G06V 20/52 (2022.01); H04N 23/617 (2023.01); H04N 23/667 (2023.01); H04N 25/60 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)
CPC G06V 20/52 (2022.01) [H04N 23/617 (2023.01); H04N 23/667 (2023.01); H04N 25/60 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
an image sensing pixel array operable to generate first data representative of an input image;
a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image;
voltage drivers;
current digitizers;
an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells when the first portion of the memory cells is programmed in the first mode to store the weight matrices used in generation of the output image;
a transceiver; and
a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array;
wherein the first portion of the memory cells programmed in the first mode to store the weight matrices is erasable and programmed in the second mode to store image data.