US 12,265,844 B2
Quality of service techniques in distributed graphics processor
Benjamin Bowman, London (GB); Fergus W. MacGarry, Cambridge (GB); Kutty Banerjee, Santa Clara, CA (US); and Pratik Chandresh Shah, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 7, 2021, as Appl. No. 17/468,312.
Prior Publication US 2023/0075531 A1, Mar. 9, 2023
Int. Cl. G06F 9/48 (2006.01)
CPC G06F 9/4881 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a graphics processor on an integrated circuit die, wherein the graphics processor includes:
at least first and second portions that respectively include shader pipeline circuitry configured to execute sets of graphics work;
first utilization circuitry configured to track execution time for sets of graphics work on the first portion of the graphics processor;
second utilization circuitry configured to track execution time for sets of graphics work on the second portion of the graphics processor;
command queue circuitry configured to store multiple different command queues, wherein the command queues include entries that store sets of graphics work;
control circuitry in the graphics processor configured to:
access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, wherein, for a given command queue, the aggregated utilization data separately indicates utilization of the first portion of the graphics processor and utilization of the second portion of the graphics processor by the given command queue; and
provide the aggregated per-command-queue utilization data in software-accessible registers; and
schedule work, from the different command queues for execution by the first and second portions of the graphics processor, based on software-specified adjustments to one or more scheduler parameters for the command queues generated in response to the aggregated per-command-queue utilization data.