US 12,265,827 B2
Forming constant extensions in the same execute packet in a VLIW processor
Timothy David Anderson, University Park, TX (US); Duc Quang Bui, Grand Prairie, TX (US); and Joseph Raymond Michael Zbiciak, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 12, 2023, as Appl. No. 18/208,444.
Application 18/208,444 is a continuation of application No. 16/846,686, filed on Apr. 13, 2020, granted, now 11,681,532.
Application 16/846,686 is a continuation of application No. 14/920,402, filed on Oct. 22, 2015, granted, now 10,620,957, issued on Apr. 14, 2020.
Prior Publication US 2023/0325189 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 7/499 (2006.01); G06F 15/80 (2006.01)
CPC G06F 9/30167 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3016 (2013.01); G06F 9/30181 (2013.01); G06F 9/3822 (2013.01); G06F 9/3853 (2013.01); G06F 9/3887 (2013.01); G06F 7/49994 (2013.01); G06F 9/3001 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3836 (2013.01); G06F 15/8053 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a functional unit; and
an instruction decoder coupled to the functional unit and configured to:
receive a first instruction specifying a first value, a first bit, and a second bit;
receive a second instruction specifying a second value;
form a third value by appending the second value to the first value;
based on the first bit, select the first value or the third value by multiplexing the first value and the third value;
based on the second bit, sign extend the selected value to form a sign extended value; and
provide the sign extended value to the functional unit for performing an operation.