US 12,265,826 B2
Systems for performing instructions to quickly convert and use tiles as 1D vectors
Bret Toll, Hillsboro, OR (US); Christopher J. Hughes, Santa Clara, CA (US); Dan Baum, Haifa (IL); Elmoustapha Ould-Ahmed-Vall, Gilbert, AZ (US); Raanan Sade, Portland, OR (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); and Alexander F. Heinecke, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,014.
Application 18/399,014 is a continuation of application No. 18/521,000, filed on Nov. 28, 2023.
Application 18/521,000 is a continuation of application No. 17/549,363, filed on Dec. 13, 2021, granted, now 11,954,489.
Application 17/549,363 is a continuation of application No. 17/549,221, filed on Dec. 13, 2021, granted, now 11,714,648, issued on Aug. 1, 2023.
Application 17/549,221 is a continuation of application No. 17/240,882, filed on Apr. 26, 2021, granted, now 11,579,880, issued on Feb. 14, 2023.
Application 17/240,882 is a continuation of application No. 16/145,066, filed on Sep. 27, 2018, granted, now 10,990,396, issued on Apr. 27, 2021.
Prior Publication US 2024/0126551 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30109 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
an instruction decoder to decode an instruction, the instruction to specify:
a two-dimensional (2D) tile storage of the processor,
either of multiple rows or multiple columns of the 2D tile storage,
multiple vector registers of the processor, and
a size of elements of the multiple rows or multiple columns of the 2D tile storage as any one of 8-bits, 16-bits, 32-bits, and 64-bits; and
execution circuitry, coupled with the instruction decoder, to perform operations corresponding to the instruction, the operations to include storing elements from each row of the multiple rows or each column of the multiple columns of the 2D tile storage to a corresponding one of the multiple vector registers as a corresponding one-dimensional (1D) vector.