US 12,265,823 B2
Trace cache with filter for internal control transfer inclusion
Ilhyun Kim, Portland, OR (US); Niket K. Choudhary, Santa Clara, CA (US); Muawya M. Al-Otoom, Lake Oswego, OR (US); Pruthivi Vuyyuru, Santa Clara, CA (US); and Ronald P. Hall, Cedar Park, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 14, 2023, as Appl. No. 18/352,323.
Prior Publication US 2025/0021333 A1, Jan. 16, 2025
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30032 (2013.01) [G06F 9/3808 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
processor circuitry configured to execute control transfer instructions;
prediction circuitry configured to predict directions of control transfer instructions;
trace cache circuitry configured to identify and store traces of instructions that satisfy one or more criteria, including that a given trace includes at least one internal taken control transfer instruction; and
filter control circuitry configured to:
for a given internal control transfer instruction in a trace stored in the trace cache circuitry, adjust a counter in a first direction in response to the given control transfer instruction executing toward the next portion of the stored trace and adjust the counter in a second direction in response to the given control transfer instruction executing away from the next portion of the stored trace; and
prevent inclusion of the given control transfer instruction as an internal instruction of traces in the trace cache in response to the counter reaching a threshold in the second direction.