US 12,265,779 B2
Clock aware simulation vector processor
Ramesh Narayanaswamy, Palo Alto, CA (US); Subramanian Ganesan, Cupertino, CA (US); and Dinesh Madusanke Pasikku Hannadige, Dodanduwa (LK)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/555,204.
Claims priority of provisional application 63/127,581, filed on Dec. 18, 2020.
Prior Publication US 2022/0198120 A1, Jun. 23, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/12 (2020.01)] 14 Claims
OG exemplary drawing
 
1. A processing system comprising:
a flow processor configured to generate instructions based on an input signal associated with a circuit design; and
an evaluation system electrically coupled with the flow processor, where the evaluation system is configured to receive the instructions and perform operations of the circuit design based on the instructions, the evaluation system comprising:
instruction memory circuitry configured to receive the instructions from the flow processor and generate control signals;
interconnect circuitry electrically coupled to the instruction memory circuitry, where the interconnect circuitry is configured to receive the control signals and a plurality of values, and route the plurality of values based on the control signals, each of the plurality of values having one of four states; and
operation circuitry electrically coupled to the interconnect circuitry and the instruction memory circuitry, the operation circuitry comprising value memory circuits and evaluation circuits, the operation circuitry configured to:
receive the plurality of values and the control signals;
perform one or more operations of the circuit design with the plurality of values based on the control signals, wherein the control signals indicate a value of the plurality of values used by the evaluation circuits to perform the one or more operations and are used to select a value memory circuit of the value memory circuits to be written to by the evaluation circuits; and
output operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.