US 12,265,776 B2
Identifying test coverage gaps for integrated circuit designs based on node testability and physical design data
Anurag Jindal, Austin, TX (US); Kapil Narula, Austin, TX (US); Rahul Kalyan, Austin, TX (US); and Hongkun Liang, Beijing (CN)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Oct. 6, 2021, as Appl. No. 17/450,093.
Claims priority of application No. 202011165581.6 (CN), filed on Oct. 27, 2020.
Prior Publication US 2022/0129613 A1, Apr. 28, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01)] 16 Claims
OG exemplary drawing
 
1. A method for determining test coverage for a circuit design, the method comprising:
obtaining node testability data and physical location data for each node of a plurality of nodes in a circuit design;
determining one or more low test coverage areas within the circuit design comprising untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes;
generating test coverage data for the circuit design comprising at least an identification of the one or more low test coverage areas, wherein generating the test coverage data includes:
determining, based on the node testability data and the physical location data, at least one of a set of modules or a set of submodules of the circuit design within the one or more low test coverage areas, wherein the at least one of a set of modules or a set of submodules comprises the untested nodes; and
including at least an identification of the at least one of a set of modules or a set of submodules in the test coverage data; and
updating the circuit design based on the one or more low test coverage areas identified in the test coverage data, wherein updating the circuit design increases test coverage in at least one of the one or more low test coverage areas.