US 12,265,775 B2
Semiconductor device with reduced power
Shih-Wei Peng, Hsinchu (TW); Ching-Yu Huang, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,810.
Application 18/362,810 is a continuation of application No. 17/578,069, filed on Jan. 18, 2022, granted, now 11,797,745.
Claims priority of provisional application 63/215,604, filed on Jun. 28, 2021.
Prior Publication US 2024/0020453 A1, Jan. 18, 2024
Int. Cl. G06F 30/30 (2020.01); G06F 30/392 (2020.01); H01L 27/02 (2006.01); G06F 119/18 (2020.01)
CPC G06F 30/392 (2020.01) [H01L 27/0207 (2013.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A flip-flop device comprising:
a first latching circuit including:
a first transmission circuit positioned in a first row of p-type and n-type transistors; and
a second transmission circuit positioned in one or more second rows of p-type and n-type transistors adjacent to the first row of p-type and n-type transistors;
a second latching circuit including:
a third transmission circuit positioned in the one or more second rows; and
a fourth transmission circuit positioned in the first row; and
a first gate conductor extending at least partially across the first row and extending at least partially across the one or more second rows,
wherein
each of the first and second rows includes a plurality of conductive patterns coupled to the respective p-type and n-type transistors,
an entirety of the conductive patterns extends between two power rails at a total of three locations evenly spaced between the power rails, the middle location being a midpoint between the power rails, and
the first gate conductor is configured to transmit one of a first clock signal or a feedback signal of the flip-flop device.