US 12,265,768 B2
Integrated circuit verification device, integrated circuit verification method, and non-transitory computer readable medium
Yohei Kojima, Kawasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 9, 2022, as Appl. No. 17/654,127.
Claims priority of application No. 2021-102948 (JP), filed on Jun. 22, 2021.
Prior Publication US 2022/0405451 A1, Dec. 22, 2022
Int. Cl. G06F 30/333 (2020.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/333 (2020.01) [G06F 30/33 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit verification device comprising:
a condition property information generation unit configured to generate a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file;
an exclusion code generation unit configured to generate, from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied; and
an exclusion code comparison unit configured to generate a second exclusion code list from a difference between the exclusion code and the first exclusion code list, wherein
the exclusion code comparison unit:
determines whether or not there is a first condition property and a second condition property in the plurality of condition properties with which at least some pieces of uncovered code in the second exclusion code list are the same as each other, and
extracts a condition property including a signal close to an input from among the first condition property and the second condition property when there is the first condition property and the second condition property.