US 12,265,732 B1
Refresh during power state changes
Jean J. Chittilappilly, Maynard, MA (US); Kevin M. Brandl, Austin, TX (US); Jing Wang, Austin, TX (US); and Kedarnath Balakrishnan, Bangalore (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/375,030.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0658 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0671 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processor operable to be coupled to a memory, comprising:
a memory operation array for storing memory operations for a first power state of the memory;
a controller responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected;
a refresh logic circuit that generates refresh cycles periodically for the memory; and
a selector for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.