US 12,265,731 B2
Partial row refresh in a memory device
Subham Panda, Balasore (IN); Muzaffaruddin Mohammed, Hyderabad (IN); Venkatesh Petnikota, Kurnool (IN); Sri Ananda Sai Jannabhatla, Hyderabad (IN); and Jyothi Ramidi, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 13, 2023, as Appl. No. 18/351,909.
Prior Publication US 2025/0021263 A1, Jan. 16, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0658 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0673 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller coupled to a memory array through a data bus and configured to access data stored in the memory array through the data bus, the memory controller configured to couple to a host device through a channel and configured to perform operations comprising:
obtaining, from the host device through the channel, partial row refresh information associated with a first row in the memory array, wherein the partial row refresh information includes an indication of a percentage of the first row to be refreshed; and
refreshing a portion of the first row in the memory array based on the partial row refresh information.