US 12,265,729 B1
Enhanced write buffer flush scheme for memory devices with high density storage memory architecture
Vamsi Krishna Sambangi, Vizianagaram (IN); Sai Naresh Gajapaka, Hyderabad (IN); Venkatesha M Iyengar, Bengaluru (IN); Madhu Yashwanth Boenapalli, Hyderabad (IN); and Sai Praneeth Sreeram, Anantapur (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 16, 2024, as Appl. No. 18/413,889.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller:
coupled to a write buffer and configured to access data stored at the write buffer, the write buffer having a single-level cell (SLC) memory architecture;
coupled to a memory module through a first channel and configured to access data stored at the memory module through the first channel, the memory module having a higher storage density memory architecture than the write buffer; and
coupled to a host device through a first interface and configured to communicate with the host device over the first interface,
the memory controller configured to cause the apparatus to:
detect a flush operation associated with the write buffer;
detect, during the flush operation, a command for placement into a command queue associated with the host device; and
prioritize the flush operation by causing the host device to place the command in a wait queue and maintaining the flush operation.