an input/output (I/O) control circuit, coupled to the flash memory controller through the specific communication interface;

a command register, coupled to the I/O control circuit, for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit;

an address register, coupled to the I/O control circuit, for buffering address information sent from the flash memory controller and transmitted through the I/O control circuit;

a memory cell array, at least having a first plane and a second plane which is different from the first plane;

at least one address decoder, coupled to the memory cell array;

a status register, coupled to the I/O control circuit; and

a control circuit, coupled to the logic control circuit, the memory cell array, the address register, the command register, and the status register, for controlling the at least one address decoder to read out more page data of multiple page units from a specific block in the memory cell array to determine whether the multiple page units are empty pages in response to a specific boundary check command signal or a specific boundary check set-feature signal sent from the flash memory controller via the specific communication interface, to determine a boundary page position of the specific block and transmit the boundary page position from the flash memory device into the flash memory controller;

wherein determining whether the multiple page units are empty pages is performed within the flash memory device and not performed by the flash memory controller; the control circuit is arranged for controlling the at least one address decoder to read out page data of page units from specific blocks at multiple planes in the memory cell array to determine whether the page units are empty pages in response to multiple boundary check command signals sequentially sent from the flash memory controller via the specific communication interface; the multiple boundary check command signals comprises a first boundary check command signal and a second boundary check command signal; the first boundary check command signal carries a first block address of a first plane, and the second boundary check command signal carries a second block address of a second plane; the first block address is identical to or different from the second block address.