CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |
1. A system comprising:
a non-volatile memory device;
a volatile memory device configured to store a mapping data structure that maps a zone of a plurality of zones of logical block address (LBA) space to a physical address space of the non-volatile memory device, wherein the zone comprises a plurality of LBAs that are sequentially mapped to a plurality of physical addresses of the physical address space;
a processing device coupled to the non-volatile memory device and the volatile memory device, the processing device to perform operations comprising: creating a logical transfer unit (LTU) corresponding to an LBA received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of the zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA; and
a hardware accelerator coupled the volatile memory, the hardware accelerator to perform operations comprising:
retrieving, from the volatile memory device, an LTU identifier associated with the LTU;
determining a zone identifier (ID) based on the LTU identifier;
retrieving, from the mapping data structure, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space that includes the plurality of physical addresses; and
storing, to the volatile memory device, the metadata for use used in determining and utilizing the physical address to perform a read operation specified by the read request.
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