US 12,265,724 B2
Data access ordering for writing-to or reading-from memory devices
Sourabh Dongaonkar, Portland, OR (US); and Jawad B. Khan, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 2, 2021, as Appl. No. 17/337,314.
Prior Publication US 2021/0286551 A1, Sep. 16, 2021
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
circuitry to receive a request to store data as a part of a matrix in a memory device;
circuitry to allocate address mappings to the data in a portion of the memory device, wherein the allocate address mappings to the data in the portion of the memory device is based on a number of rows that end in a block boundary;
circuitry to store the address mappings for access with a read operation;
circuitry to cause storage of the data into the memory device according to the address mappings; and
circuitry to, based on receipt of a read request to access a row of data that is not stored in the matrix, provide the read request to the memory device and without translation of a memory address.