US 12,265,723 B2
Per channel thermal management techniques for stacked memory
Chang Kian Tan, Bayan Lepas (MY); Ru Yin Ng, Bayan Lepas (MY); Saravanan Sethuraman, Bayan Lepas (MY); and Kuljit S. Bains, Olympia, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2021, as Appl. No. 17/485,343.
Prior Publication US 2022/0011960 A1, Jan. 13, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/061 (2013.01); G06F 3/0676 (2013.01); G06F 3/0677 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
input/output (I/O) circuitry to receive channel temperature information from a plurality of stacked memory dies, the channel temperature information to indicate a temperature of a channel of a memory die of the plurality of stacked memory dies; and
circuitry to:
throttle row commands to the channel at a first rate based on the channel temperature information, and
throttle column commands to the channel at a second rate based on the channel temperature information.