US 12,265,718 B2
Simplified raid implementation for byte-addressable memory
Derek Alan Sherlock, Fort Collins, CO (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed on Oct. 23, 2023, as Appl. No. 18/492,374.
Application 18/492,374 is a continuation of application No. 17/558,260, filed on Dec. 21, 2021, granted, now 11,822,802.
Prior Publication US 2024/0045607 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0689 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A first media controller, comprising:
one or more processors; and
a non-transitory computer-readable medium storing programming for execution by the one or more processors, the programming comprising instructions to:
receive a first media-access request targeting a first data block of a first data stripe, the first data stripe being distributed across multiple storage devices and comprising a first parity block and multiple first data blocks, a first storage device of the multiple storage devices being coupled to the first media controller and configured to store the first data block of the first data stripe; and
perform a first media-access sequence in response to the first media-access request, performing the first media-access sequence comprising generating a first tracker entry to delay, for a duration of a first tracker-occupied event, performance of another media-access sequence during a critical section of the first media-access sequence, the critical section being a portion of the first media-access sequence in which the first data stripe may be inconsistent.