US 12,265,717 B2
Storage access communications and data placement for improved performance and reduced write amplification
Luca Bert, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 20, 2023, as Appl. No. 18/337,819.
Claims priority of provisional application 63/390,936, filed on Jul. 20, 2022.
Prior Publication US 2024/0028230 A1, Jan. 25, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, in a memory sub-system, a stream of write commands from a host system;
maintaining, by the memory sub-system and for the stream, a cursor identifying a first superblock of the memory sub-system and a location within the first superblock available to store data for the stream;
mapping, by the memory sub-system using the cursor, first logical addresses of a first segment of the stream sequentially to physical addresses in the first superblock of the memory sub-system to store data of write commands in the first segment;
allocating, by the memory sub-system, a second superblock of the memory sub-system to update the cursor in response to the first superblock being full and in response to a further write command in the stream;
mapping, by the memory sub-system using the cursor, second logical addresses of a second segment of the stream, starting from a logical address of the further write command, sequentially to physical addresses in the second superblock to store data of write commands in the second segment;
receiving, by the memory sub-system, commands from the host system to delete data from logical addresses; and
reclaiming, by the memory sub-system, a third superblock after having received commands to delete entire data from the third superblock without reclaiming a partially erased superblock through moving data from a portion of the partially erased superblock.